1. Field of the Invention
The present invention relates to an electrostatic discharge (ESD) protecting circuit and a method for fabricating the same, capable of consuming a high voltage or overcurrent applied to a semiconductor circuit device and thereby protecting the circuit device from the high voltage or overcurrent, and more particularly to a transistor of such an ESD protecting circuit comprising an asymmetric charge coupled MOS thick film transistor having a highly-doped buried layer, capable of improving the characteristic thereof and the resistance characteristic to an ESD impact, and to a method for fabricating the same.
2. Description of the Prior Art
As semiconductor devices have a higher integration degree, the resistance characteristic to ESD impact is degraded because of the use of a lightly doped drain (LDD) structure and a shallow junction and the use of titanium silicide (TiSi.sub.2). For fabrication of semiconductor devices of the next generation , however, it is required that there be improvements in resistance characteristics to ESD impact.
For satisfying such a requirement, there has been proposed an ESD protecting circuit adapted to protect an internal circuit of a semiconductor circuit device from an external ESD impact. FIG. 1 is a circuit diagram illustrating such an ESD protecting circuit.
As shown in FIG. 1, the ESD protecting circuit includes a first transistor 100 which is a thick film transistor adapted to be turned on when a positive ESD impact is applied to an input of the circuit device. At the turned-on state, the first transistor 100 provides a bypass for allowing the positive ESD impact to be bypassed without giving any damage to the internal circuit. The first transistor 100 has a threshold voltage of about 15 V or greater. The ESD protecting circuit also includes a second transistor 200 which is a thin film transistor serving as a bypass for bypassing a negative ESD impact.
The present invention concerns the fabrication and application of the first, thick film transistor of the above-mentioned ESD protecting circuit. As representative of conventional techniques about the above-mentioned fabrication and application, there have been two known techniques which are illustrated in FIGS. 2 and 3, respectively.
In the case of FIG. 2, the traditional thick film transistor 100 includes doped source/drain contact regions (source/drain electrodes) 24 and a gate oxide layer 28. By this connection structure, an N type channel is formed in a portion of a P type substrate 21 disposed beneath the gate oxide layer 28, when a positive ESD impact is externally applied to the transistor 100. The N type channel serves as a bypass for bypassing the positive ESD impact. At this time, the thick film transistor 100 is operated in an inversion mode. As a result, the N type channel is formed on the upper surface of the P type substrate. This results in a limitation on the maximum channel width.
Consequently, the conventional technique has a drawback of limiting the maximum current discharged through the channel because electrons can flow (in the direction of arrow 30) only through the channel inverted. In other words, there is a limitation on removal of the ESD impact. Due to the residue of ESD impact over the limit, the ESD protecting circuit itself or the internal circuit of the circuit device may be damaged. As a result, the ESD protecting circuit may not achieve its protection function.
Furthermore, where a particular metal such as titanium silicide is used in fabrication of a highly integrated semiconductor device to reduce the metal-substrate contact resistance, the resistance characteristic to ESD impact is greatly reduced.
For solving the drawback encountered in the above-mentioned traditional thick transistor structure, the technique illustrated in FIG. 3 has been proposed which uses a thyristor.
The technique of FIG. 3 utilizes a rapid bipolar characteristic of the thyristor having a PNPN structure. In this case, complex process steps are additionally required for fabrication of the thyristor, even though a superior resistance characteristic to ESD impact is obtained.
For this reason, such a transistor employing the thyristor has seldom been used in the case of a mass-produced semiconductor devices.
In FIGS. 2 and 3, the reference numerals 22 and 32 denote gate oxide films, respectively, reference numerals 25 and 35 denote electrodes, respectively, while the reference numerals 23, and 33 denote insulating films, respectively. Also, the reference numeral 34 denotes a source/drain, 36 a well, 37 a p+ region and 38 a gate oxide layer. The device shown in FIGS. 2 and 3 include gate electrodes, but these gate electrodes are not shown simultaneously with the source/drain electrodes due to the nature of the cross sectional views.